应用MicroBlaze软核作为CPU的硬件平台,在此平台上设计了基于AXI总线的通用实时时钟IP核。给出了创建IP核的过程和导入IP核的方法。介绍了实时时钟的IP核结构,给出了IP核的结构框图。介绍了实时时钟的原理,给出了实时时钟各个模块的核心代码。

MicroBlaze was used as embedded hardware system.In this embedded hardware system,the real time clock IP core was based on AXI bus.The method of creating and importing the IP core was provided.The structure of the IP core was introduced.At the same time the structured flowchart of the IP core was provided.The theory of the real time clock was introduced,and the core code of the modules was provided.

SoC（System-on-a-Chip）芯片设计中,由于芯片测试引脚数目的限制以及基于芯片性能的考虑,通常有一些端口不能进行测试复用的IP（Intellectual Property）核将不可避免地被集成在SoC芯片当中.对于端口非测试复用IP核,由于其端口不能被直接连接到ATE（Automatic Test Equipment）设备的测试通道上,由此,对端口非测试复用IP核的测试将是对SoC芯片进行测试的一个重要挑战.在本文当中,我们分别提出了一种基于V93000测试仪对端口非测试复用ADC（Analog-to-Digital Converter）以及DAC（Digita-l to-Analog Converter）IP核的性能参数测试方法.对于端口非测试复用ADC和DAC IP核,首先分别为他们开发测试程序并利用V93000通过SoC芯片的EMIF（External Memory Interface）总线对其进行配置.在对ADC和DAC IP核进行配置以后,就可以通过V93000捕获ADC IP核采样得到的数字代码以及通过V93000采样DAC IP核转换得到的模拟电压值,并由此计算ADC以及DAC IP核的性能参数.实验结果表明,本文分别提出的针对端口非测试复用ADC以及DAC IP核测试方案非常有效.

IP cores without I/O multiplexing are typically unavoidable to be embedded into SoC due to the necessary consid-erations such as pin constraint and performance optimization during the design stage .Hence ,one of the serious challenges for SoC testing is how to effectively test IP cores without I/O multiplexing because the ports of IP cores without I/O multiplexing cannot be directly connected to the ATE channels .In this paper ,we propose test methods for ADC and DAC IP cores without I/O multiplex-ing using V93000 ATE respectively .In order to test the ADC and DAC IP cores without I/O multiplexing ,test programs are firstly developed and loaded into V93000 to configure the two cores via EMIF bus .Then the digital codes and the analog voltage values re-spectively converted by ADC and DAC IP cores of SoC are captured by V93000 for performance parameter calculation .Experimen-tal results show that the proposed methods are effective .

利用SOPC技术,将8051 IP核与CAN IP核有机融合,提出了一种创新型的控制器局域网(CAN)节点设计方案。介绍了如何使用硬件描述语言(HDL)实例化8051 IP核和CAN IP核,描述了这两个软核的接口类型及它们之间的握手细节。编写测试程序,综合整个工程,并将生成的工程代码下载至FPGA运行。结果表明:使用SOPC技术设计的CAN节点通信良好,利用可重配置的IP核技术,可以实现更加复杂的功能,系统的设计也会更加灵活、稳定、可靠。

SOPC technique is used to organize them and demonstrate the combination of CAN( Control er Area Network) IP Core and 8051 IP Core. Then this paper proposes an innovative approach to design the CAN node, introduces the use of the Hardware Description Language ( HDL) for implementing 8051 IP Core and CAN IP Core, describes the interface type of these two soft-core and the details of the handshake between them makes a test procedure,integrates the whole project and sends the object code to FPGA. The results indicate that the CAN node which is designed to use the SOPC technology is perfect in the communication,and with the help of reconfigurable IP core technology, multiple functionalities can be realized and the design of this system is of more flexibility,stability and reliability.

本文提出了一种产生混沌序列的新方法:在FPGA嵌入式系统中设计了一个用于产生混沌序列的IP核。传统的混沌序列生成方法是通过软件编程实现,序列的生成速度较慢且占用资源较多。本文设计了一个IP核,利用硬件实现混沌序列的产生,提高了序列的产生速度。本文在Virtex-Ⅱ Pro开发平台上,运用EDK工具搭建了一个FPGA嵌入式平台,并添加了设计的IP核,验证了IP核的功能。

A new approach for the design of chaotic sequence generator is proposed:designing an IP core to produce chaotic sequences on a FPGA Embedded platform.Most of conventional methods of generating chaotic sequences are realized by software approach,which is slow and consumes a lot of resources.This paper represents a design of IP core, which can produce chaotic sequences quickly by hardware approach.On the Virtex-II Pro development platform,the IP core is added to the embedded system which is built by the EDK software,and its function is veriifed.

针对两相仪用步进电机，提出了一种基于可编程片上系统的步进电机驱动控制器IP核的设计方案。设计和实现了各功能模块，并将其封装成了IP核。仿真和实测结果表明，所研究设计的IP核具有启动、停止、改变方向、加／减速以及细分等功能，可应用于各种两相步进电机驱动控制系统，特别是多步进电机应用系统，大大减少了重复设计的工作量，且运行稳定可靠。

This paper presents a design of stepping motor drive controller IP core based on programmable system on chip ( SOPC ) for the two-phase stepping motor used in instruments .All function modules are realized and packaged into an IP core .The simulation and test results show that the IP core achieved the function of start, stop, speed-up, speed-down and micro-stepping, etc.The proposed IP core can be applied in a variety of two-phase stepping motor drive control systems , especially the multiple stepping motor applications .The workload of repeated design is greatly reduced and the operation is stable and reliable .